New PCIe 6.0 technology is in the works, and according to nonprofit electronics industry consortium PCI-SIG, it’s in the final draft stages. While it’s still early days, new information suggests that PCIe 6.0 will offer speeds as high as 128GB/s, beating the previous gen by a mile. The current standard is still PCIe 4.0, with the 5th generation of the technology yet to be released. Comparing PCIe 6.0 to the PCIe 4.0 standard produces even better results — PCIe 6.0 will be up to four times faster than the technology we are using now.
PCI Express has to go through five stages before being approved: The concept stage, first draft, compete draft, final draft, and release stage. The Complete Draft stage was reached a little less than a year ago with version 0.7 of PCIe 6.0.
The current version is 0.9, meaning that PCIe 6.0 is nearing the 1.0 version it will receive upon completion. This final draft version allowed a select crowd of members of the PCI-SIG to test and review the new standards provided by this technology.
PCIe 5.0 will offer much lower speeds per pin than what we are likely to see from PCIe 6.0. The upcoming generation of this technology offers data transfer rates of up to 32GT/s per pin, while PCIe 6.0 may offer up to 64GT/s. It will also be capable of conducting transfers in all directions on its x16 interface.
The key metrics assembled by PCI-SIG include latency of less than 10 nanoseconds, an improved power efficiency when compared to the previous generation, and full backward compatibility with PCIe 1.x through PCI 5.0. In order to achieve the requirements, manufacturers are expected to utilize pulse amplitude modulation with four levels (PAM-4). An alternative is adopting signaling, which is a technology found in GDDR6X memory.
In order to achieve the expected transfer speeds combined with high efficiency, PCIe 6.0 will offer forward error correction at the lowest possible latencies. All of these efforts are made in order to meet the expectations set for the PCIe technology, which is that the in and out bandwidth should double once every three years with each new release.
While all of this sounds exciting on paper, there are still some obstacles for the developers and manufacturers to overcome, namely the cost and the power requirements of the die. It’s hard to predict when the new technology will be released, but it’s worth noting that we’re not even using PCI Express 5.0 just yet.
It will start being utilized with the release of Intel Alder Lake, expected later this year, so while it is coming along nicely, it’s still a long way until PCIe 6.0 will be seen anywhere in consumer hardware.
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