According to a slide provided by the PCI-SIG during Intel’s show, PCI Express 1.0 was launched in 2003 pushing data at 2.5 gigatransfers per second across the motherboard bus. If you’re not familiar with that term, gigatransfer refers to gigabits of encoded data moving back and forth each second via numerous “lanes” from the motherboard to an attached card. Naturally, the higher the number, the faster these “cars” of data are traveling. The “x16” portion points to 16 physical lanes as oppose to “x4,” which only provides four.
That said, when PCI Express 2.0 was introduced in 2006 with a 5GT/s rate, a single lane was capable of pushing five gigabits of encoded data per second in one direction, thus a single back-and-forth process from the CPU to the card pushed 10 gigabits of encoded data per second. Note all of this numbering applies to encoded data, as eight bits of encoded data is transferred as 10 bits.
As for the rest of the PCI Express rollout, version 3.0 with a rate of 8GT/s was introduced in 2010 … which was six years ago. The latest PCI Express spec launching next year will push 16GT/s, and apparently the PCI-SIG is already toying around with a new 5.0 spec based on its distributed roadmap. The good news with the upcoming 4.0 spec is that thanks to the data transfer rate, SLI bridges will likely be a thing of the past, which is probably one of the big reasons why Nvidia is moving away from supporting multiple graphics cards in one system. Consumers will see PCI Express storage solutions move their data even faster, too.
Because PCI Express 4.0 provides twice the bandwidth of the previous generation, device makers can essentially reduce the number of physical lanes if they want to offer the same bandwidth seen with their PCI Express 3.0 solutions. For instance, a PCI Express 4.0 card with eight lanes would have the same data rate as a PCI Express 3.0 card with 16 lanes. The 4.0 spec will be backwards-compatible, too.
Reports surfaced back in June that chips utilizing the upcoming PCI Express 4.0 spec were heading to foundries despite 4.0 not finalizing until next year. Cadence, PLDA, and Synopsys even showcased devices during the recent PCI-SIG annual developer conference based on the upcoming spec. As reported by Heise Online, Synopsys was at Intel’s conference this week displaying a system utilizing the Mellanox card.
Unfortunately, the first generation of AMD’s “Summit Ridge” processor family likely won’t support PCI Express 4.0, nor will the first rollout of Intel’s seventh-generation “Kaby Lake” desktop processors. However, things look good on the mobile front, as PCI-SIG president and chairman Al Yanes said that “mobile is the spot” right now due to the increased scalability of PCI Express 4.0, which improves its overall penetration into the mobile market.
“There’s at least one or two solutions,” Yanes told PC Magazine during Intel’s conference this week. “[But] I’d like to have more. We’re trying to evangelize a bit better on our low power [usage in 4.0]. Flash, NVMe plays well; storage, I think we kind of got that one. So I think mobile is the spot.”
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