As revealed during a 30-minute session at the convention, Power9 is a new CPU architecture that’s slated to begin rolling out in the second half of 2017. It’s built for what IBM CEO Ginni Rometty calls the “cognitive era,” a time period that will “redefine the relationship between man and machine.” Previous generations of Power-based processors focused solely on the enterprise sector and eventually Big Data management.
That said, the Power family of processors has seemingly been around forever, and it’s no surprise that IBM is still cranking out Power-branded processors 16 years after their debut. However, you won’t find IBM’s Power9-based processors in mainstream desktops and notebooks. They compete directly with products offered by AMD (Opteron) and Intel (Xeon) in the x86-based server market. If anything, the general consumer will see the benefits of IBM’s Power9 architecture through cloud services that rely on data centers utilizing IBM’s technology.
According to IBM, Power9 was developed to handle the evolution of artificial intelligence, cognitive computing, and analytics. It will be served up (no pun intended) in two designs: a “scale-out” model optimized for two CPU sockets on the motherboard, and a “scale-up” model built for multiple CPU sockets. Typically, server motherboards can range from a single socket up to four.
Additionally, IBM’s scale-out and scale-up models will feature two processor configurations each: a chip packed with 24 SMT4 processor cores that’s optimized for the Linux ecosystem, and a chip packed with 12 SMT8 processor cores optimized for the PowerVM ecosystem. Notice the CPU processor core names: The SMT8 features eight threads (lanes) whereas the SMT4 only has four.
Power9 will be based on 14nm FinFET process technology. This is a method for fabricating processors, as it shrinks transistors and other components down to fit within a small, defined area. The smaller the transistors, the more that can be crammed into the same defined space. That in turn increases performance and reduces the chip’s overall power draw. The FinFET (aka Fin Field Effect Transistor) aspect means that the processing model uses a specific transistor that relies on a thin, silicon “fin.”
In a slide provided during IBM’s presentation, the company showed that the “Scale Out” model will depend on direct attach memory, meaning there will be eight direct DDR4 ports. The other “Scale Up” model will rely on buffered memory, utilizing eight buffered channels. This latter setup will provide up to 230GB per second of sustained bandwidth whereas the former will only provide a sustained bandwidth of 120GB per second.
The company also revealed that Power9 will have a reduced pipeline compared to Power8, knocking the “fetch to compute” process down by five cycles, which essentially means improved performance in applications that use modern coding. Other benefits introduced by the Power9 architecture include advanced branch prediction, local pipe control of load/store operations, and even a new instruction set providing support for emerging algorithms, broader data type support, energy and frequency management, and acceleration for emerging workloads.
Technical info regarding IBM’s Power9 processor architecture arrives after AMD recently revealed all the naked details of its “Zen” processor core technology that will first be used in “enthusiast” desktop processors in 2017 followed by server-based chips. Thus, it’s no surprise that IBM had lots to say about Power9 during this week’s convention.
Until Power9 officially arrives, we’ve got all the juicy technical details about the new architecture displayed during the Hot Chips 28 convention in a gallery embedded below.
