How do urban planners and building developers cope as more and more people move to cities? There are a few things they might do. To begin with, they could physically make the city larger, widening its borders to cover surrounding land so as to accommodate more houses. They might also build houses closer together, squeezing more single- and double-story buildings onto each street. At a certain point, however, there’s really only one option: You build upward by creating tower blocks that can house hundreds on a patch of land that would otherwise fit only a tiny fraction of that number.
This, in essence, is a similar problem to the one faced by chip designers. Moore’s law states that, every couple of years, the number of components that can be inexpensively crammed onto an integrated circuit doubles. The power of Moore’s law is undeniable. In 1971, for example, Intel released the 4004, the world’s first commercially available microprocessor, packing 2,300 transistors onto a single chip. By comparison, in 2021, Apple’s A14 processor boasts a mind-boggling 11.4 billion transistors. To put that in perspective, if the top speeds of cars had followed a similar trajectory, modern vehicles would be driving at faster than the speed of light.
When it comes to delivering next-generation chips, chipmakers, like urban planners, have three options available: They can make the chips themselves bigger to support more components; they can shrink the components and pack them in more tightly; or they can build upward. For the most part, it’s the second option that has been pursued. Components have grown steadily smaller, to the point where modern transistors are each around a dozen atoms in size and squeezed into proximity so close that it’s measured in nanometers.
But this can’t carry on indefinitely. At some point soon, we’ll need to rethink the way we create more powerful, next-generation chips. Many researchers around the world are working on that problem right now. However, one international team of investigators has a particularly fascinating idea — and it involves using all-around wonder material graphene to build new transistors unlike any seen today. (Hint: They’re the skyscrapers of the transistor world.)
On a video call, the de facto way presentations take place in 2021, Manoj Tripathi, from the U.K.’s University of Sussex, shows me an image. It’s a picture of a flat blue surface, with what looks like a single wave rising up on an otherwise serene plane. If I didn’t know any better, I could easily be convinced that Tripathi was an oceanographer. In fact, he’s a research fellow in the university’s School of Mathematical and Physical Sciences with a big interest in semiconductors, two-dimensional materials, and flexible electronics. His latest project, this one, combines all three.
Graphene is a single layer of graphite, the soft material that’s commonly found in pencil lead, with a 1-atom-thick (or, perhaps, thin) structure of carbon atoms arranged in a hexagonal, honeycomb-like structure. Graphene is the material of seemingly boundless uses. It’s among the strongest materials in the known universe, with a strength that’s approximately 100 times that of steel. It’s a great superconductor, allowing electrical current to flow through it with zero resistance. Heck, it can even act as the world’s finest sieve, as it’s capable of filtering the salt out of saltwater or the color out of scotch. That’s just scratching the surface.
“One thing that is rarely discussed is that it’s also very flexible,” said Tripathi. “We are targeting that [quality for this project]. What I mean by ‘flexible’ is that you can bend it, you can crumple it, you can do something like that.” To illustrate the “something like that,” Tripathi produces a cloth he uses to clean his computer and mimes wringing it out.
Many materials are, of course, flexible. But the reason graphene’s flexibility is so exciting is that when wrinkles appear in its surface, it changes the flow of electrons, which in turn alters the material’s electrical properties from point to point. Using a technique referred to as atomic force microscopy, the researchers are able to measure the effects of different patterns of wrinkles in the graphene. By leaning into these different kinks, which trigger different electrical and mechanical properties, the researchers can create very small transistors made of graphene.
This is where the metaphor of the multistory building factors in. “That’s exactly what we’re doing,” Tripathi said. “Chip sizes are getting reduced each year, [but] there is a problem accommodating transistors … What’s the solution? We have to use the z-axis — the multistory buildings — to accommodate a higher number of transistors per unit area.”
Although the height variability would be observable under a microscope, it would be entirely invisible to the naked eye. In fact, the transistor created using this technique is approximately 100 times smaller than a comparable one on a regular silicon chip.
At present, these are still the relatively early stages of the project. There’s still a lot more to be done before this process makes its way into actual chips. One problem, for instance, concerns the consistency of the wrinkles, something that would be crucial to get right for consistency of chip yield.
The researchers have been able to make rows of wrinkles with graphene by using patterned molds. However, there are still challenges. “The generation of the wrinkle is not a problem,” Tripathi said. “The generation of consistent wrinkles is a problem.” He noted that a wrinkle intended to give a vertical height of four nanometers shakes out as “sometimes eight nanometers, sometimes three nanometers.”
Tripathi said that solving this “is achievable, but we have to think out of the box.” Fortunately, “we have a team of eminent scientists from [the] U.K., U.S.A., Greece, and Italy” to help with this. He was confident that the approach could, in the hands of the right people, provide a runway for extending Moore’s law significantly.
“To give you an answer in one word, I think it is possible,” he said. The researchers aim to have a prototype chip up and running within five years.
A paper describing the work was recently published in the journal ACS Nano.