Western Digital said on Monday that it began a pilot production of a new 3D NAND chip in Yokkaichi, Japan. This chip packs three bits of data into memory cells that are spread across 64 stacked layers, providing 512 gigabits of storage capacity. The chip is an industry first and the result of a collaboration between Western Digital and Toshiba. It’s expected to go into mass production sometime during the second half of 2017.
Western Digital and Toshiba first introduced 3D NAND with 64 layers in July. Dubbed as “BiCS3,” the technology is unlike standard “2D” NAND that relies on storage cells distributed horizontally across physical space like crowded city blocks. Instead, 3D NAND places cells on layers and stacks these “floors” vertically like tall skyscrapers. This enables higher storage capacities because 3D NAND isn’t limited to the physical boundaries of the actual memory chip (die). Thus, the sky is seemingly the limit for 3D NAND.
According to Toshiba, BiCS Flash technology enables memory chips with a smaller size due to the manufacturing process and circuit technology. Even more, the spaces between each memory cell are wider than those in traditional 2D NAND products so that the storage product can write data faster. These wide spaces also reduce the amount of “noise” each cell experiences from other neighboring cells on the layer, making the stored data more reliable.
The 64-layer 3D NAND introduced last summer only supported 256 gigabits of storage capacity per chip. The new model doubles the density, meaning resulting products will have double the storage capacity in the same form factor than what was provided with the initial 64-layer 3D NAND technology. Details regarding how Western Digital and Toshiba made this increased storage density possible will be provided in a technical paper during the International Solid-State Circuits Conference.
Toshiba said in November that it would begin constructing a “state-of-the-art” fabrication facility in Yokkaichi in February to expand its production of BiCS Flash products. The fab will be built in two phases to mirror Toshiba’s financial investment against the current market trends. The first phase isn’t expected to be complete until the summer of 2018.
“The new fab will have a quake-absorbing structure and an environmentally friendly design that includes LED lighting throughout the building, plus the latest energy saving manufacturing equipment,” Toshiba said. “It will also introduce an advanced production system that uses artificial intelligence (AI) to boost productivity.”
The new 512Gb BiCS3 Flash chip will increase the capacities of devices that rely on Flash-based storage such as smartphones, tablets, solid- state drives, USB storage drives, and so on. For smartphones and tablets, the technology means these devices can offer the same amount of capacity as before, but on smaller memory chips, thus enabling manufacturers to use the extra physical space to install larger batteries. The capacities can be larger too because of the stacked nature of 3D NAND.
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