Skip to main content

3D-chip technology seeks to pack artificial intelligence into smaller spaces

When it comes to the brains of the PC — the central processing unit, or CPU — today’s technology is in some ways significantly advanced over yesterday’s. CPUs are much faster than they used to be, but the traditional metric for measuring performance improvements, Moore’s Law, has been challenged lately.

Moore’s Law specifically states that the number of transistors in an integrated circuit will double every two years, meaning that processing performance will continue to steadily increase. As we have reached the limits of current processor manufacturing technology, however, Moore’s Law is threatened — right when advancements in artificial technology require even faster and smaller CPUs. That is precisely why new 3D-chip technology being developed by Stanford and Massachusetts Institute of Technology researchers is particularly important.

Complicating matters is that AI is no longer centralized in massively powerful data centers. Increasingly, AI is being pushed out to edge devices that need to stand on their own. Self-driving cars and personalized medicine are two example of applications that require extremely powerful decentralized CPU capabilities.

The researchers are developing technology that could solve the current performance squeeze by packing more computer components into single chips. Most computers today are made up of many chips that are connected together on motherboards using electrical circuits. Even at electronic speeds, the distance between chips limits the speed at which these chips — CPUs and memory, for example — can communicate and process information.

The new 3D-chip technology will help solve that problem by creating single chips that contain both CPUs and memory and thus reduce or eliminate the lag created with current designs. In order to create these chips, the researchers are adapting carbon nanotubes made of graphene to stack integrated circuits one over another. That is impossible with silicon-based circuits due to the high temperatures required in their production — using carbon nanotube circuits enables the creation of chips at much lower temperatures.

As MIT assistant professor of Engineering and Computer Science Max Shulaker puts it, “Circuits today are 2D, since building conventional silicon transistors involves extremely high temperatures of over 1,000 degrees Celsius. If you then build a second layer of silicon circuits on top, that high temperature will damage the bottom layer of circuits.” Carbon nanotube circuits can be built at temperatures below 200 degrees Celsius, allowing circuits to be stacked without damaging lower levels.

It’s not just CPUs and memory that can be stacked together to make a single 3D chip. Other technologies such as sensors can also be built in, making for even more powerful single-chip solutions. While the details are quite complex, the results could be revolutionary. Not only would Moore’s Law gain new life, but future AI could be built into increasingly smaller devices as well.

Editors' Recommendations