A new technology introduced by Taiwan Semiconductor Manufacturing Company (TSMC) could boost the power of graphics cards by Nvidia and AMD without making them physically larger. The technology is called wafer-on-wafer, and mimics 3D NAND memory technology used in modern solid-state drives by stacking layers vertically rather than spreading the hardware horizontally across the printed circuit board, which would require additional physical space.
So what’s a wafer? Unlike your favorite snack, it’s a thin slice of polished semiconductor material that serves as the foundation for a crisscross of layered copper wires that convey electricity, and the transistors that are the heart of the processor. The wafer and mounted components are cut by a diamond saw into single chips and placed into the physical processor package you see when you break open the desktop.
Right now, graphics chips produced by Nvidia and AMD rely on a single wafer. But TSMC, the largest dedicated independent semiconductor foundry on the planet, discovered a way to stack two wafers in a single package. The upper wafer is flipped over onto the lower wafer, and then both are bonded together. Moreover, the upper wafer contains the in/out connection piercings (aka thru-silicon vias), thus the duo is packaged using flip-chip technology.
According to TSMC partner Cadence, the technology could see two sets of wafers connecting to each other in a cube-shaped package using what’s called an interposer, an electrical interface that routes one connection to another. More than two wafers could be stacked vertically as well, with all but one wafer sporting the in/out thru-silicon vias connections.
While this is a lot of tech talk, it’s basically describing how graphics chips can be scaled vertically, not horizontally, using TSMC’s technique. Not only can you cram more cores into a single graphics chip, the communication between each wafer would be extremely quick.
Thus, instead of tweaking an architecture and rebranding the product as a new family, manufacturers could potentially stack two or more current GPUs on a single card as a product refresh. The operating system would detect it as a single card, and not as a multi-GPU configuration.
With 3D NAND, memory cells are stacked vertically and connected together via makeshift data elevators. This method enables manufacturers to provide additional storage capacity while staying within the same physical constraints. This design is faster, too, given the data travels up and down the memory tower rather than hunting down its destination using horizontal “city streets.”
The problem with stacking processor wafers may be in the overall manufacturing yields. One of two wafers could pass, but because the other wafer is bad, both would be discarded. This method could prove to be too costly on low-yield products and would need to be used on production nodes with high manufacturing yields, like TSMC’s 16nm process technology.
TSMC introduced its wafer-on-wafer technique during its symposium in Santa Clara, California. The company also revealed a partnership with Cadence for 5nm and 7nm+ process technology for high-performance and advanced mobile computing.
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