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Samsung Develops 70-nm DRAM Technology

From Samsung’s press release:

Samsung Electronics announced that it has developed the industry’s first “CVD aluminum” process technology, the very latest 70-nanometer node DRAM process technology employing the Chemical Vapor Deposition or CVD method.

The CVD aluminum process technology is one of the key interconection technologies in DRAM manufacturing process. It involves forming conducting films by turning metal organic source , including aluminum, into particles through chemical reactions and depositing them on a wafer surface, and then creating wiring for the interconnecting circuits.

Existing DRAM circuit-wiring processes have employed the Physical Vapor Deposition or PVD method in which thin films are formed by turning solid-state materials into particles. However, due to the problem of “ void ” in which the deposition is not evenly made on the wafer surface, thus causing problems in the circuit properties, this PVD method has been difficult to apply in the 90-nano-or-less scale processes.

However, if the CVD aluminum process technology is employed, not only is the problem of cavitations addressed, but also the electrical properties of circuit-wiring are dramatically improved, making it an essential process technology in manufacturing 70 nano meter DRAM s .

Furthermore, if this CVD aluminum process technology is employed, analysis shows that it would reduce costs related to circuit-wiring process by up to approximately 20 percent, as it does not require planarization (etch-back) and cleaning process , which have been required until now in circuit-wiring process.

As the application of high-performance DRAM s expands from the PC to mobile and consumer electronics products, it is imperative to develop nano-scale DRAMs in order to respond to the ever-increasing demand. However, until now there has been little progress in the development of next generation DRAM processes in the industry.

On the other hand, Samsung Electronics has been the industry leader in unveiling advanced nano meter – node DRAM process technologies and design technologies such as metal capacitor technology, three-dimensional transistor design technology, and inlaying technique design technology, thereby taking the lead in next generation nano meter -semiconductor technologies and building a foundation for maintaining its competitive advantage in the future.

In particular, the CVD aluminum process technology was submitted as a technology paper at the VLSI (Very Large-Scale Integrated-circuit) Technology Symposium and IEDM (International Electron Device Meeting), the world’s most prestigious semiconductor symposiums, and gained a highly favorable reception. The company has also applied for 15 international patents related to this technology.

Samsung Electronics has already secured 90 nano meter 512Mb DRAM samples by applying the CVD aluminum process technology and plans to unveil 70 nano meter DRAM employing this process technology b y the end of the year.

[Reference explanations]

 DRAM process

The DRAM process is largely comprise d of four stages : circuit design , wafer fabrication , assembly , and inspection. Among them, the essential core process is the wafer fabrication process which comprises photolithography , etching , circuit-wiring , diffusion , ion implantation , and cleaning. Each process is selectively repeated several times, depending on different products.

 Planarization process

Planarization is a process to smooth the wiring interconnects of wafers to facilitate wiring between layers. Chemical Mechanical Polishing (CMP) and etch-back process are mainly used in the planarization process.

•  Chemical Mechanical Polishing (CMP) is an abrasive process using tiny-particled chemical slurries and a circular action by fixing the wafer to an apparatus to polish the surface of the wafer smooth.

•  The etch-back process is a process to make the wafer surface smooth by selectively eliminating unnecessary particles from the surface through the dry etch process.

 VLSI (Very Large Scale Integrated-circuit) Technology Symposium

The VLSI Symposium is one of the three most internationally recognized symposiums on semiconductors, along with IEDM (International Electron Device Meeting) and ISSCC (International Solid-State Circuits Conference). Since the first symposium jointly organized by the United States and Japan was held in 1981, the symposium has been held around June every year alternately in Hawaii or Kyoto. The world’s leading semiconductor manufacturers such as Intel, NEC, Toshiba and Infineon are the main participants in the symposium.

The selection process for published papers is extremely strict, as only the most outstanding papers among the hundreds of papers submitted by semiconductor manufacturers from all around the world are adopted for publication at the symposium.

 IEDM (International Electron Device Meeting)

IEDM is the world’s most prestigious conference related to micro- and nano-electronics. It is held alternately in Washington D.C. and San Francisco every December. Major areas covered in the conference include silicon and non-silicon device technologies, opto-electoronics, micro-electro mechanical systems and molecular electronics.

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